ADLINK Technology PCI-7200 Spécifications télécharger pdf (Page 36)

26 •• Operation Theorem

4.3 External Clock Mode

The digital input is clocked by external strobe, which is from the Pin

19 (I_REQ) of CN2 (PCI-7200) or Pin 24 of CN1 (cPCI-7200). The

operation sequence is very similar to Timer Pacer Trigger. The only

difference is the clock source.

1. The external input strobe is generated from outside device, and

go through the Pin 19 (I_REQ) of CN2 and to latch the digital

input.

2. The digital input data are saved in FIFO after an I/O strobe

signal is coming in.

3. The data saved in input FIFO will be transferred to main memory

on your computer system directly. This is controlled by bus

mastering DMA control, this function is supported by PCI

To Digital Input Trigger

Latch Digital

Input Data

Digital Input FIFO

Bus mastering

DMA data Transfer

PC's Main Memory

Pin 19 of CN2

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ADLINK Technology PCI-7200 Spécifications Page 36